Analysis of Latency and Throughput of 2D Torus Topology using Modified XY Routing Algorithm

Network-on-Chip (NoC) is a packet switched onchip communication network designed using a layered methodology i.e. “routes packets, not wires”. It is an efficient on chip communication architecture for System on Chip (SoC) architectures. NoCs solved the disadvantages of SoCs and are scalable. Each route in NoC includes some routers and it takes a few clock periods by passing a router. When the network is in congestion, the package transmission will produce much more time delay. So adopting an appropriate routing algorithm to get the balance between the time delay and throughput rate becomes the key problem. In this paper we tried to solve that problem using torus topology with our modified XY routing algorithm. We used NIRGAM simulator for analysis of latency and throughput of modified XY routing algorithm for 2D torus topology. 3x3 network size used for analyze the performance. We consider all tiles as source, all tiles as destination and vary the packet size & traffic used is Constant Bit Rate (CBR) random traffic. It is found that packet size increases then latency/packet increases and throughput (in Gbps) also increases but latency/flit decreases.